The Information Processing Lab is engaged in designing and implementing algorithms of information technology and signal processing. The implementation of these methods in terms of certain computer-architectures and the integration as system-on-chip components is analysed for different technical applications. While designing these new methods, the interaction of algorithms and architectures becomes particular relevant but also the constraints of the concrete analysed technical applications (signal-model, noise, power consumption) will be incorporated to the project-concept. Considered technical applications are: adaptive filters and adaptive antenna-fields, detection- and estimation problems in the field of mobile communications systems.
Due to the rapidly growing complexity of modern Signal processing algorithms, it is necessary to run parts of the algorithm on special hardware coprocessors. This is true for stationary applications such as e.g. high-definition television (HDTV), but also in the mobile area where the end device has to support more and more different radio standards (GSM, UMTS, WLAN, DVB ,...), and functions such as MP3 or video playback at the same time. Here is needed a partial implementation in hardware to ensure a low power consumption.
Modern FPGAs make it possible to reconfigure the hardware in the ongoing operation. The hardware can be directly adjusted to the required configurations to improve the speed or the efficiency of executing algorithms.
The work in this area will cover the design and adaptation of algorithms for the most efficient processing through the development of the mentioned Coprocessors, to the integration of reconfigurable hardware in operating systems such as Linux.
Furthermore, in the Signal Processing Lab an own FPGA development board was developed. More about this here (german). Students who are interested in the further development of this board are always welcome.
An integrated electronic circuit that can be reprogrammed arbitrarily is the standard microprocessor. However, the microprocessor cannot comply with the high data rates and real time requirements in many signal processing and communication applications. Therefore, it is necessary to design ASICs (application specific integrated circuits) for these specific applications. Unfortunately, a typical ASIC cannot be reprogrammed at all.
The goal of this project is to include reconfigurable components in the architecture of ASICs such that the fabricated integrated circuit can be reconfigured to compute various algorithms. Of course, it is not possible to design such a reconfigurable device for arbitrary algorithms. However, it becomes possible if we restrict ourselves to algorithms which algebraically belong to the same class.
Here, we concentrate on classes of algorithms that are frequently encountered in signal processing and communication applications. Basically, we try to identify a class of algorithms (and their application domains) that are very related from the point of their mathematical formulation, i.e. they are based on the same algebraic roots. Since parallel and pipelined architectures for these algorithms are usually obtained by linear algebraic transformations, the respective architectures show the same general structure.
During this project the design of efficient algorithms and their sustainable implementation for third and fourth generation mobile radio systems is investigated. The main focus at the third generation is on `joint` or `multiuser` data detection in TD-CDMA and WCDMA systems. Joint detection plays a key role in the third generation plans since it provides the promised spectral efficiency gain.
The aim for the fourth generation is to accomplish an explicit higher transfer rate as in the third. Keeping this in mind an aim is to develop efficient algorithms, which will on the one hand meet the conditions of the standards of a 4G system, and on the other hand be kept common in order to be suited to solve signal processing problems in different systems. Currently, shared and efficient receiver algorithms in divers transfer systems e.g. OFDM and single-carrier systems are in the focus of the assay.
Main approach is the exploitation of special structural characteristics in the mathematical formulation of the problem, and the search and practice of opportunities to parallelize the solution process.
The aim of this project is to create a model that allows power estimations of various algorithms for a range of target architectures. The model should be applicable to several different architectures.
There are generally a large number of algorithms available for any one problem in information or signal processing (for example, more than ten for multiuser detection in CDMA based mobile radio systems). The goal is to select the best algorithm according to the developed power consumption model.
These explorations are also the basis for developing new methods for designing algorithms. The model leads to modifications of the basic arithmetic operations, the communication structures, the preprocessing, the allocation management and partitioning, etc that all lead to improved power consumption of the algorithms and architectures.
Approximation methods are widely encountered in signal processing applications. Usually these methods are used to approximate functions or signals. However, finite word length or accuracy of results can also be related to approximation methods. Here we try to identify how approximations can be used with respect to a reduced complexity of computer architectures.
 Hardwaredevelopment: Aptix-Systemexplorer The Aptix System Explorer is employed in processes for research as well as for teachings. The picture above shows the Systemexplorer with 2 FPGAs, one LCD- Display as output-module and two joysticks as input-modules. This allows the realisation of simple circuits and systems (e.g. simple video games) can be depicted. For the processing and testing of those algorithms, being developed in current research projects, extensive test data will be exchanged by a direct broadband transport connection with a workstation (hardware-in-the-loop simulations). |
The number of standards used in wireless transfer systems is increasing (eg GSM, UMTS, WLAN,
Bluetooth, WiMAX). A support of all standards by dedicated hardware in mobile terminals will
be always unacceptable.
To increase the Terminal's velocity, the base-band signal processing will be done in software,
which allows a fast reconfiguration of the Terminal according to the required standards.
As part of the project, a transciever based on a DSP (Digital Signal Processor) for the DRM
(Digital Radio Mondiale) broadcasting standard will be developed, which can be easily modified
because of the modular structure, for example, to verify new algorithms.
In parallel, appropriate algorithms that distinguish for their adaptive properties in terms
of mathematical complexity and performance will be developed.
This will allow that the complexity of signal processing algorithms (for example, the channel
decoding) adapts to the transmission conditions.
Consequently, the energy efficiency of mobile terminals can be increased, leading to smaller
designs and respectively longer operation times.
The rising demand for data transmission rate in mobile communications systems makes high demands on the computing power of mobile terminals. To achieve the necessary data throughput, it is aimed to implement the base band singal processing in parallel architectures. These include both traditional hardware architectures (ASIC, FPGA) and multi-processor systems. In addition, the parallel signal processing allows energy-efficient implementations, as high speeds can be avoided. To be able to use the aforementioned advantage, a description of signal processing tasks through algorithms with parallel structures is necessary. As part of this and previous projects will be therefore developed parallel descriptions for common baseband operations in OFDM and CDMA systems (such as detection, channel decoding, FFT). Hier will be investigated especially the possibility of overlapping block signal processing for various applications.